This invention relates to an improved method and apparatus for generating programmable timing signals. More particularly, this invention relates to a digital system and method for generating precisely positioned timing signals independent of system component variations due to manufacturing process variations or temperature variations and independently of clock edge location.
The proliferation of large scale integrated (LSI) and very large scale integrated (VLSI) circuits result in an ever increasing use of electronic functions within the integrated circuit. Accordingly, testing devices utilized to evaluate these electronic functions have an increasing burden to evaluate multiple functions, and as such, must be versatile and must accurately perform multiple test functions at high speed. The signal generator is an integral part of the testing device. Such a test device requires a re-configurable and accurate signal generator which has the capability of generating several master clock signals simultaneously.
Historically, signal generators have utilized resistor-capacitor (RC) networks to establish master clock signal frequencies. These analog based frequency generators are very sensitive to resistance value changes over temperature, and to parasitic capacitance. Additionally, manufacturing variability may affect RC values. For example, digital clock circuits may employ inverters in series to establish an operating frequency. These inverter circuits are affected by parasitic capacitance between respective inverters and also changes in output impedance of each respective inverter; both of these factors affect the frequency of the generated master clock signal. As such, digital circuits may be subject to the same temperature and manufacture variability as analog based systems. It is thus desirable the have a programmable clock circuit that functions independently of manufacturing variability and temperature.
Historically, programmable clock circuits have used external clock references, wherein the clock reference may be sensitive to noise and thus result in output master clock signal jitter as noise is detected in the circuit. It is desirable to employ a signal generating circuit that utilizes an external clock reference but is not susceptible to external noise.